Sensors - February 2001 - Time-Interleaved Data Converters

Photo 1. High-energy, particle physics uses powerful facilities, such as the electron linac at the Stanford Linear Accelerator Center. Detecting and analyzing high-energy particles usually requires sophisticated and ultra-fast data acquisition equipment. To accommodate the need for high-speed data capture with off-the-shelf components, designers are often forced to develop their own detector and data logger circuits by interleaving multiple data converters to increase the system clock and data capture speed.

Time-interleaving high-speed A/D converters can dramatically multiply the sampling speed of a data acquisition system, but it becomes a tricky and complex chore at high sampling speeds.

or high-speed applications, time interleaving increases the overall sampling speed of a system by operating two or more data converters simultaneously (see Photo 1). This may sound simple and straightforward, but it requires more effort than merely running two A/D converters (ADCs) in parallel. Let's start by comparing the sampling rate of a time-interleaved system with that of a single converter. As a rule of thumb, operating M ADCs in parallel increases the system sampling rate by an approximate factor of M. Thus, the sampling, or clock, frequency for an interleaved system that hosts M ADCs (each ADC operates on the same clock frequency as its adjacent neighbors) can be described as follows:

Figure 1 shows a simplified single-channel, time-interleaved DA system in which two ADCs double the system's sampling rate.

Figure 1. This single-channel data acquisition (DA) system uses two A/D converters (ADCs) and track-and-hold amplifiers (T/H) to double the system's overall sampling speed. Such an approach can allow designers of high-speed speed DA systems to use off-the-shelf ADCs rather than custom-made, high-speed converters.

This rate (f_{SYSTEM_CLK}) is a clock signal that is twice the rate of f_CLK1 = f_CLK2. Because f_CLK1 is delayed with respect to f_CLK2 by the period of f_{SYSTEM_CLK}, the two ADCs alternately sample the analog input signal to produce an overall sample rate equal to f_{SYSTEM_CLK}. Each converter operates at half the sampling frequency.

How Does Time Interleaving Work?
T typical time-interleaved system can be explained by analyzing the operation of an N-bit, two-step flash converter. ADCs featuring clock speeds greater than several hundred megahertz often have a multistep, time-interleaved architecture rather than a single-step, direct-conversion (pure flash) architecture (see the sidebar "Flash Conversion").

To increase the sampling rate of an ADC whose comparators are already running at maximum speed, you must extend the number of upper (coarse) and lower (fine) quantizer blocks. You can achieve this by implementing an N-bit coarse ADC and two time-interleaved, Næbit fine ADCs (see Figure 2).

Figure 2. Two fine quantizers (FQ1 and FQ2) and one coarse quantizer (CQ) are the basic building blocks for an interleaved, two-step A/D converter (ADC) architecture. While CQ is always sampling and converting, FQ1 and FQ2 are designed to operate in alternating cycles. This enables the ADC to roughly double its sampling speed.

The coarse quantizer (CQ) determines the upper bits (most significant bits, or MSBs), and the fine quantizers (FQ1 and FQ2) set the lower bits (least significant bits, or LSBs) of the digital output.

The CQ and FQ1 blocks are connected to the input terminal during the first sampling step, but only the CQ samples and digitizes at that time. In a second step, FQ1 and FQ2 use information from CQ to generate the reference levels that enable them to perform a fine quantization. The LSBs are digitized during the time it takes to sample and perform a conversion with CQ, and interleaving takes place when CQ samples the second time.

When the first sampling and conversion process is complete, the input is sampled and digitized by CQ and FQ2. While FQ2 is processing the second sample, CQ is sampling a third time. When the second sample quantization is finished, the third sample is then converted by FQ1. CQ is always sampling and converting, but FQ1 and FQ2 sample and digitize on alternate cycles. As this procedure repeats, it roughly doubles the overall sampling speed of the two-step ADC system.

What Should Be Considered When Time Interleaving?
It may be tempting to push the operational limits of interleaved ADCs, but this method cannot be turned into a successful experiment unless various limitations are considered.

Bandwidth Limitations. Applications that call for higher sampling speeds usually deal with high-frequency input tones, so a data converter with an input bandwidth of half the sampling speed would not be suitable for interleaving. Fortunately, most high-speed data converters include track-and-hold (T/H) amplifiers whose full-power and small-signal bandwidths are significantly higher than the Nyquist criterion (f_SAMPLE/2) calls for.

Offset and Gain Errors. The channel-to-channel matching of offset and gain in separate ADCs is not trimmed, so you have to be concerned about gain and offset mismatches between ADCs in a time-interleaved system. If one ADC shows an offset and the other a gain error, the digitýzed signal represents not only the original input signal but also an error in the digital domain. An offset discrepancy causes a signal phase shift in the digitized signal, and gain mismatches show up as differences in signal amplitude. It's better to choose ADCs with integrated gain and offset error corrections for interleaving designs or include external circuitry that allows correction of these mismatches.

Nonlinearities. Integral nonlinearity (INL) is the deviation of the actual transfer function from a straight line, either in LSBs or in percent of full-scale range. Individual ADCs often have INL errors of ±1, but in an interleaving system, such errors can easily multiply, causing output-code errors that are similar to the offset and gain problems already discussed. Nonlinearity introduces distortion into the system, which degrades dynamic parameters, such as signal-to-noise and distortion, effective number of bits, and total harmonic distortion.

Clock-Phase Jitter and Noise. The signal used as a system clock should have the lowest possible phase noise. A D-type flip-flop in a divide-by-two configuration can reduce the otherwise stringent requirement for a precise 50% duty cycle. It's a good idea to choose a clock circuit cýmmensurate with the signal source's frequency range, amplitude, and slew rate. A low slew rate on the digitized signal also relaxes the jitter requirement on the clock. But if the slew rate is high, you have to minimize the clock jitter. For a full-scale-amplitude sinusoidal input signal, the maximum suggested SNR caused by clock jitter only is:

You can overcome most of the errors described here by using a well thought out circuit design and layout, a suitable selection of data converters and digital post-processing, and calibration procedures in the time domain. Unfortunately, this approach is complex and entails extra cost, a lengthy calibration, and precise mathematical analysis.

Application
This article's theoretical approach can be confirmed by evaluating and analyzing the performance of an actual circuit. The test setup suggested in Figure 3, for instance, is based on the use of two MAX1444 evaluation boards from Maxim (evaluation boards let you measure channel-to-channel or lot-to-lot mismatches as well as their effect on the performance of a time-interleaved system).

Figure 3. This approach to an interleaved circuit uses two readily available evaluation kits for high-speed A/D converters. Because of lot-to-lot variations in the manufacturing process of these kits, a careful selection of termination and connection techniques between the signal sources and the board is recommended.

The MAX1444 offers the lowest speed grade (40 Msps) available in Maxim's new 10-bit, 3.3 V, single-supply, high-speed data-converter family. Because it's highly unlikely that two off-the-shelf test boards will be precisely matched, the signal sources (the clock and analog-input signal generators) should be carefully connected to the boards.

This article has offered some basic theoretical ideas and a quick overview of what to consider in designing time-interleaved systems. The circuit in Figure 3 has not yet been tested. An evaluation of the circuit and a comparison between it and a higher speed off-the-shelf ADC is in progress. These results will be published as soon as they are available.

For Further Information
Hofner, Tanja C. 1999. "Pipeline ADCs Come of Age," Engineering Journal 33:3-9.

Johns, D. and K. Martin. 1997. Analog Integrated Circuit Design. New York, John Wiley & Sons, Inc.

van de Plasche, R. 1994. Integrated Analog-to-Digital and Digital-to-Analog Converters. Boston, Kluwer Academic Publishers.

Flash Conversion
A/D Converters (ADCs) based on direct-conversion, or flash, architectures are extremely fast and perform their multibit conversion directly. Intensive analog design, however, is necessary to manage the high numbers of comparators and reference voltages required for this architecture. A pure flash converter with N-bit resolution has 2^N-1 comparators connected in parallel. The reference voltages for these comparators are set by a resistor network and spaced 1 LSB = V_FS/2^N apart, where V_FS represents the converter's full-scale input range and N is its resolution.

A change of input voltage usually produces a change of state in more than one comparator output. These output changes are combined in an encoder-logic unit (2^N-1-to-N encoder) that produces a parallel N-bit output from the converter. Although flash converters are the fastest types available, their resolution (a 1-bit increase in resolution requires doubling the number of comparators) is usually constrained by die size, input capacitance, and power consumption introduced by the large number of internal high-speed comparators. In addition, the repetitive structure of flash converters demands precise matching between the parallel comparator sections because any mismatch can cause static error, such as increased input offset voltage.

In addition, flash ADCs are prone to sporadic and erratic outputs (sparkle codes). Sparkle codes have two major sources: "thermometer-code bubbles" and metastability in the 2^N-1 comparators. Mismatched comparator delays can turn a logical 1 into 0 (or vice versa), causing the appearance of "bubbles" in an otherwise normal thermometer code. Because the ADC's encoder unit cannot detect this error, it generates an out-of-sequence code that appears as a "sparkle" output. Most new data converters include additional latches that minimize or eliminate this problem.