
May 2003
A Digitally Programmable
A digital technique for converting a 0%–100% PWM signal to a different maximumtominimum duty cycle offers linearity and temperature characteristics superior to those achieved by conventional analog conversion methods.
Asad M. Madni, Jim B. Vuong, and Philip T. Vuong Most modern sensors provide their outputs in two basic forms, analog and digital. Among the formats for digital outputs are:
Although several PWM circuits have been developed that provide 0%–100% duty cycle to represent the sensor’s fullscale output, specialized applications require the start and stop duty cycles to be very specific, e.g., 5%–95% to represent the total output. This article describes a circuit design technique that produces a programmable PWM output. Although designed for 5%–95% duty cycle range for a noncontact angular position sensor (NCAPS) [1,2], the technique can be adapted to any start or stop duty cycle for virtually any sensor.
Theory of Operation
For example, when a 5%–95% PWM is desired, all it takes is to precisely adjust the offset and limit the gain of the sensor’s output amplifier to correspond to the desired minimum and maximum values. However, if a sensor’s natural output is a PWM signal, as is true of the NCAPS, then it is a different story. The NCAPS is an angular position sensor based on a transceiver concept. Its output is generated by comparing the phase information that is proportional to the angular position of a rotor (coupler) to a fixed reference phase signal. The difference between these two signals generates a PWM output (see Figure 2).
It should be noted, however, that the output waveform is dependent on the type of phase detection technique used. For example, edge detection will generate a PWM with sawtooth characteristics; an exclusive OR will generate a triangular PWM. Since the output PWM signal is proportional to the position of the rotor/coupler, a 0%–100% PWM signal represents the angular position of 0°–360°. Either an analog or a digital method can be used to convert a 0%–100% PWM signal into a different startandstop value (in this case, 5%–95%). In the analog approach, the PWM signal must be converted into a analog signal by using a simple RC circuit or an active lowpass filter circuit; the analog signal is then compared to a triangular waveform to generate the final 5%–95% signal. It should be noted, though, that this method can adversely effect the sensor’s linearity due to the PWMtoanalog conversion and the temperature susceptibility of the analog components. The digital method, on the other hand, can be immune to these problems. A block diagram of a digitally programmable PWM converter is shown in Figure 3.
The converter’s major components are counters and comparators. Counters are used to digitize the pulse width of the signal, and comparators to create the required signal in digital form. To convert the incoming PWM signal (f_{i}) to a desired PWM signal output, it is necessary to count the pulse width of the incoming signal with a faster and known frequency (f_{1}). It then can be used to derive a new PWM signal output with the same frequency as the input signal, but with (P_{1}%–P_{2}%) duty cycle. The calculation for frequency f_{1} is given by:
The total number of counts (x_{1}) for COUNTER1, COUNTER2, and COUNTER4 is:
and the total number of counts (x_{2}) for COUNTER3 is:
where:
= period of the system clock
= period of the input PWM signal The relationship between the input and output duty cycle is given by the following transfer function:
where:
When an external PWM signal of frequency f_{i}, with a 0%–100% duty cycle, is fed to the converter, COUNTER1 is triggered; it begins counting at the rising edge of this signal and stops counting at the falling edge. When the PWM signal goes low, it will latch the current value (k_{1}) of COUNTER1 through latch1 and reset COUNTER1 as well. The latched value is compared with the output value of COUNTER2 through the A comparator in order to generate an internal 0%–100% duty cycle PWM signal with frequency f_{1}. This internal PWM signal is further decoded by COUNTER3. The rising edge of f_{1} triggers COUNTER3 to start counting, and when it goes low it latches the current value (k_{1}') of COUNTER3 through LATCH2 and resets COUNTER3 as well. This latched value corresponding to the duty cycle of f_{1} is added to a P_{1} set value using an adder, and the resultant sum (k_{2}) is compared to the output value of COUNTER4. When the sum is greater than the current value of COUNTER4, the output of the B comparator will stay high; otherwise it will be low until COUNTER4 overflows. The value of COUNTER4 always contains an additional count corresponding to the P_{1} PWM set value so that it can maintain the minimum and maximum duty cycles (P_{1} and P_{2}) for the output PWM signal. In other words, the output duty cycle is a proportional value between the sum of the current count of COUNTER3 and P_{1} set value to the total number of counts of COUNTER4. In this manner, the converter will generate a PWM signal that has the same frequency as the input PWM signal (i.e., f_{i}) with P_{1}–P_{2} duty cycle. A timing diagram of converting a 1% and 99% PWM input signal is shown in Figures 4 and 5.
Illustration of a Typical Conversion
To measure the pulse width of a 2 kHz PWM signal with COUNTER1, we need to determine the number of counts for the counter. If CLK1 is 8 MHz, then the period is t_{0} = 0.125 µs (^{1}/_{8} MHz). A 2 kHz signal has a period t_{1} = 500 µs (1/2 kHz), so the total number of counts needed for COUNTER1, COUNTER2, and COUNTER4 is x_{1} = t_{1}/t_{0} = 500/0.125 = 4000. The total number of counts for COUNTER3 is x_{2} = x_{1} × (P_{2} – P_{1}) = 4000 × (0.95 – 0.5) = 3600. The calculation for frequency f_{1} equals 1/[(P_{2} – P_{1}) × t_{1}] = 1/[(0.95 – 0.5) × 500 µs] = 2.22 kHz. Since a counter with 4000 counts is used to decode the 2 kHz PWM signal, a second counter with the same counting value must also be used for decoding the 2.22 kHz PWM signal. To match a 2.22 kHz PWM signal with a 2 kHz PWM signal in the same manner, a clock source with CLK2= 4000 × f_{1} = 4000 × 2.22 kHz = 8.88 MHz is applied to this counter. After all, a 12bit counter
Summary
Acknowledgment
References
2. ———. April 2001. “The Next Generation of Position Sensing Technology, Part 2: Differential Displacement and Linear Capabiities,” Sensors, Vol. 18, No. 4: 6165. Dr. Asad M. Madni, a member of the Sensors Editorial Advisory Board, is President and Chief Operating Officer; Jim B. Vuong is Senior Staff Engineer; and Philip T. Vuong is Project Engineer, BEI Technologies, Inc., Sylmar, CA; 8183647215, bei1madni@aol.com (Madni); jvuong@beitech.com (J. Vuong); pvuong@beitech.com (P. Vuong).



