Acceleration Data Acquisition
Using a Converter

Acceleration data acquisition systems can profit from built-in
A/D converters that provide anti-aliasing functions
while keeping the cost well under control.

John C. Cole,
Silicon Designs, Inc.

Most acceleration measurement applications use a successive approximation (SA) analog-to-digital (A/D) converter, preceded by an anti-aliasing filter, to convert the data into a collectible form. The resulting digital data are then either analyzed in sampled form or further processed to reduce their storage size. Often, a microprocessor is used to compute spectral content by means of a fast Fourier transform (FFT) or the root-mean-square (rms) value of the sampled data. Unfortunately, the budget for such applications is often exceeded when the cost of the requisite anti-aliasing filters is factored in. If the anti-aliasing function could be incorporated into the microprocessor portion of the system, high performance could be retained at a low overall system cost.

The objectives of this article are to describe the advantages of an acceleration data acquisition (DA) system that uses a A/D converter, and the way anti-aliasing functions can be incorporated into a low-cost acceleration DA system. The performance of such a system will also be compared with a conventional design.

Conventional A/D System

The anti-aliasing filter portions of conventional SA A/D-based systems have been widely discussed and as such are easily designed (see Figure 1). The problems with these filters are that they typically require a fair amount of PCB board space; they must be built with precision resistors and capacitors; and, in some cases, they require precision tuning of the component values. They are also not easily changed.

The sensor is the device that measures the acceleration, converting that property into an electrical parameter such as voltage, current, resistance, or capacitance. The signal conditioning circuit converts the sensor output into a standardized electrical parameter such as a voltage between ­5 V and +5 V. It typically contains circuits that adjust the gain, offset, and variation with temperature of the sensor's output. It may also include an analog anti-aliasing filter that limits the bandwidth of its output to a bandwidth of interest for the signal.

An A/D converter is used to sample the output of the signal conditioner periodically at a particular rate. Most instrumentation applications use an SA A/D converter preceded by a sample-and-hold. Resolution is measured by the number of bits in the digital output of the A/D converter, typically from 8 bits to 16 bits.

Figure 1. For acceleration data collection, conventional systems use a successive approximation A/D converter to transform the sensor output into a digital word that can be read by a microcontroller or PC. A sensor can rarely be directly connected to an A/D converter without intervening--and sometimes expensive--signal conditioning circuitry.

sampling rate are preserved in the sample values. Frequency components above half the sample rate, referred to as the Nyquist frequency or Nyquist rate, are aliased or "folded" into the range between zero and the Nyquist frequency. The aliasing process essentially converts frequency components above the Nyquist frequency into noise that contaminates the signals below the Nyquist frequency. Once folding has occurred in the sampling process, aliased noise cannot be separated from the signal component by any subsequent filtering. Figure 2A is an example of an original signal spectrum, and 2B shows the spectrum after sampling. The high-frequency peak could be either from the acceleration present or from one of the noise sources mentioned above.

Anti-Aliasing Filters. Anti-aliasing filters, applied before A/D conversion, are designed to reduce the aliased noise by reducing the amplitude of frequency components above the Nyquist frequency to acceptable values. These low-pass filters are designed to pass frequencies below the Nyquist rate and reject those above it. Figure 2C shows how a filter applied to the same signal used in Figure 2A reduces the aliased noise.

Figure 2. The Nyquist theorem dictates that any signal(s) above the Nyquist frequency, such as this narrow-band, high-amplitude signal (A), will appear at a lower frequency within the band below the Nyquist frequency (B). This undesired effect can be prevented by raising the sampling frequency or filtering out any signals above the Nyquist frequency before sampling occurs (C).

Quantization or truncation noise results from the limited number of discrete values that can be measured with the number of bits in the A/D converter. The instantaneous value of this noise is the difference between the actual signal and its quantized value. It is usually modeled as a random variable with a uniform distribution over ±¹/₂ of the least significant bit (LSB). Quantization noise can be modeled as additive white noise whose rms value is equal to ¹/₆ LSB and whose power is spread uniformly over the range of zero to the Nyquist frequency.

Sampling Rate/Anti-Aliasing Filter Tradeoffs. To avoid aliasing noise, the anti-aliasing filter should have:

• A passband that includes all the frequencies of interest
• A stop band that begins before the Nyquist frequency

If we choose a sampling rate only slightly higher than twice the highest signal frequency of interest, then we need to have an anti-aliasing filter that cuts off very quickly at the Nyquist rate. Filters with a sharp cutoff at an exact frequency require a large number of operational amplifiers and highly accurate resistors and capacitors.

On the other hand, if we choose a sampling rate equal to 8­10 * the highest frequency of interest, then the filter can have a cutoff over a wide frequency range. We can in fact even allow some aliasing as long as nothing is aliased into the frequency band of interest, since we can remove it after sampling using a sharp cutoff digital filter in software.

So by increasing the sampling rate above its minimum value, we benefit by making it easier to design and implement the anti-aliasing filters. With reasonably high sampling rates, anti-aliasing filters actually may not be needed with most piezoresistive and capacitive MEMS accelerometers, since these accelerometers have a built-in two-pole mechanical filter that is typically in the 1­5 kHz range.

A/D Conversion

A/D conversion takes advantage of this tradeoff between sampling rate and anti-aliasing filter requirements to reorder the sequence of operations [1]. A is a simple 1-bit A/D converter that runs much, much faster than twice the highest frequency of interest. Its output takes only one of two values: a 1 or a 0 at each clock time. An output 1 corresponds to a positive full-scale value; an output 0 corresponds to a negative full-scale value.

A block diagram of a first order A/D is shown in Figure 3. As in an SA A/D converter, a comparator is used to determine whether the input voltage is above a threshold voltage. The differs from an SA architecture in that the error made by the digital approximation is accumulated and used in the next digital approximation. The integrator accumulates the error from the previous outputs and the difference between the current input and output. The main effects of integrating the error are that the truncation error of the 1-0 sequence does not accumulate over time, and most of the quantization noise is shifted from low to high frequencies.

Figure 3. A first order A/D converter yields a high-rate, serial stream of 1s and 0s. It consists of a difference function, an integrator, a clocked comparator, and a single-bit A/D converter. An output of a 1 signifies that the input signal is above the integration value; an output of a 0 signifies the input signal is below the integration value.

Oversampling. A converter operates much faster than twice the highest frequency of interest. In a tilt sensor, for example, only frequencies below ~10 Hz or so are of interest. The Nyquist rate for a converter operating at, say, 500 kHz is 250 kHz. The oversampling ratio is the ratio of the converter's Nyquist frequency to the highest frequency of interest, 10 Hz. In this case the oversampling ratio is 250,000:10 or 25,000.

Oversampling is beneficial in two ways. First, the very high Nyquist frequency means that even the accelerometer's built-in mechanical filter is more than enough to prevent aliasing of the acceleration data. Second, the very large quantization noise from a 1-bit quantizer is spread over the very large frequency band up to the Nyquist rate, with the result that only a small amount of the noise appears in the 0­10 Hz band of interest. In a converter, quantization noise in the low-frequency region is so minor that with a high oversampling rate and the low-pass filtering described below, the 1-bit quantizer of a has better quantization noise characteristics than a 16-bit SA A/D converter.

Decimation Filter. The high-rate stream of 0s and 1s is generally not useful for processing and storage. What is normally needed are 8- to 16-bit values at a much lower rate, say 100 Hz, a form similar to what one would get from an SA A/D converter. A decimation filter is used to make this conversion.

Counter As a Decimation Filter. The simplest form of decimation filter is a counter. The counter is initially zeroed and then turned on to count the number of 1s during a period of time. The count value is recorded and the counter is rezeroed for the next period of time. A counter is particularly useful for low-frequency applications such as level sensors, which require high resolution.

The zeros of a counter's transfer function correspond to frequencies that would alias to DC, the frequency of interest. Even for higher frequency applications, since sampling is usually done at about 8­10 * the highest frequency of interest, the frequency response is down more than an order of magnitude at the first frequency that would alias into the bandwidth of interest.

Digital Decimation Filter. A generalized decimation filter performs the same function as the anti-aliasing filter in a conventional A/D system. In a general form, it is a digital, low-pass filter that takes as its input each single-bit sample. For each input bit, which it considers either positive or negative full scale, it computes a multiple-bit output value, say 16­32 bits. Decimation by "n" is the process of using only one of every n values calculated. To reduce the 500 kHz of the above example to a 100 Hz rate, we would select only one out of every 5000 values computed by the digital filter. We can use as many of the 16­32 bits as we want to store, but the quantization noise limits the usefulness of too many bits.

Figure 4. A simple decimation filter can be realized by using a counter to simply count up the number of 1s that occur in the output of a converter over a periodic, fixed-time interval. The counter computes the average value of the signal over each interval and is therefore called a rectangular filter.

As with the anti-aliasing filter, the cutoff frequency of the decimation filter is selected to some value larger than the highest frequency of interest and lower than half the final sampling rate. In addition to filtering out those frequencies that would alias into the band of interest, it also filters the out-of-band quantization noise.

A counter, which is part of many microprocessors, can be used as a simple decimation filter. It counts the number of 1s during a time interval, T, at which time its value is recorded and the counter is reset to zero. The impulse response of this type of filter is a rectangular pulse that is zero except for the time interval 0­T, which corresponds to a frequency response of sin(2¼fT)/2¼fT (see Figure 4).

Low-bandwidth digital filters running at high rates require careful design to avoid roundoff problems since coefficients are either small or very near 1.0. This problem can be reduced by performing decimation in two steps. First, a counter is used to decimate from the rate to some intermediate rate that is high enough to avoid any aliasing. Then decimation is performed at the final rate by means of a digital filter. The filter can be designed to have near-ideal characteristics for the application, and since it is run at the slower intermediate rate, it requires much less computational power than a single-stage decimation filter.

Benefits of a System. The advantages of a system are:

• No environmental noise pickup
• Easily changed sampling rates
• Lower power consumption

First, the A/D converter is located at the sensor itself. By transferring data in digital form, between the sensor and data acquisition system, we eliminate all ambient noise pickup from hostile equipment environments. Accelerometers with a high power supply rejection ratio also reduce power supply noise in the sensor output.

A digital decimation filter can be performed in software, and its frequency response is easily altered by changing the filter coefficients. The final sampling rate and number of bits are also software adjustable. Hardware anti-aliasing filters and a fixed resolution SA A/D are not so easily changed.

The power consumption of a system can also be lower. The G-Logger Model 3310 is a battery-powered shock and vibration recorder that uses a A/D combined with a digital accelerometer described below. The first-stage decimator is located in the recorder and its output is stored in flash memory that is downloaded later to a PC. With lots of inexpensive processing capacity, the PC can compute the second-stage, high order decimation filter during or after the downloading process. Furthermore, the filter characteristics can be changed after the data are examined, an option not permitted by conventional A/D architecture.

Implementation of a System

The analog output from any type of accelerometer can be used with A/D converter ICs. Silicon Designs offers a line of miniature MEMS-based accelerometers with a built-in first order A/D converter. These devices can be connected directly to a microcomputer, such as an 80C51-generation or Microchip 17C4x to implement high-resolution, low-frequency systems at a low cost.

The Model 1010 digital accelerometer, available in full-scale ranges of 5 g, 10 g, 25 g, 50 g, 100 g, and 200 g, operates on ~1 mA of current at 5 VDC. It has over 40 dB of power supply rejection, and operates over a ­55°C to 125°C temperature range. Information on the 1010 and other Silicon Designs accelerometers is available at www.silicon designs.com

Reference

1. Steven R. Norsworthy et al. 1997. Delta Sigma Data Converters, IEEE Press.

John C. Cole is President, Silicon Designs, Inc., 1445 NW Mall St., Issaquah, WA 98027-5344; 425-391-8329, fax 425-391-0446, jcole@silicondesigns.com

Home | Contact Us | Advertise © 2009 Questex Media Group, Inc.. All rights reserved. Reproduction in whole or in part is prohibited. Please send any technical comments or questions to our webmaster.