Sensors - September 2002 - An Optical Timing System

A simple, sensor-based instrument you can build yourself derives speed data by measuring the time between two optical events.

Web-Only Figures and Listings
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  • Web Listing 1
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The simple, but complete sensor-based measuring instrument design described in this article can be used to indirectly measure the speed of a moving object by measuring the time elapsed between the interruption of two optical beams. I designed the device for measuring elapsed time ranging from milliseconds to minutes, making it useful for speed measurement in numerous applications. The design includes a display and status indicators, all digital logic required for timekeeping and control functions, and the analog signal processing necessary to interface to the infrared (IR) LEDs and photodiodes that provide the optical sensing functions.

My secondary goal was to demonstrate how programmable digital and analog ICs can be used to inexpensively implement a measurement and instrumentation system constructed with tools and materials readily available to or obtainable by a hobbyist.

There are four major subsystems in this instrument (see Figure 1): the user interface, sensor interface/receiver, counter/display logic, and master control logic.

Figure 1. The use of programmable analog and digital ICs allows complete subsections of the instrument to be implemented in single ICs, providing a clean, modular design.

The user interface consists of a 7-digit LED numeric display that shows the elapsed time; several status LEDs; and two pushbutton switches, reset and arm. Pressing reset clears the display; arm tells the device to wait for the first beam to be broken. Detailed descriptions of the other three subsystems will be provided further on. Complete schematics of this project can be seen as Web Figure 1 and Web Figure 2.

Sensor Interface/Receiver
Each optical beam, generated by an IR LED pulsed at 10 kHz (see Figure 2, waveform A), requires an independent analog processing channel.

Figure 2. The receiver signal processing chain amplifies, filters, and recovers low-level electrical signals from a photodiode. Also shown are waveforms at different points in the chain.

Pulsing the beams makes them easier to detect in the presence of constant background light. Additionally, the pulses driving each channel are out of phase with one other to reduce the possibility of interchannel crosstalk.

For high brightness, the LED is not driven directly by the output of the master control complex programmable logic device (cPLD) but rather by a discrete transistor switch that can provide up to 100 mA of drive current. Strongly illuminating the LED is desirable because a greater optical signal both increases the maximum allowable range between the LED and photodiode receiver, and also results in less false triggering. When no object is blocking the optical path between the IR LED and the photodiode, the photodiode will generate a small current proportional to the incident light. The photodiode current is then converted to a voltage signal (waveform B) by a load resistor.

Blocking the DC component of the detected signal with a high-pass filter reduces the influence of incident ambient light, and also facilitates detecting the incoming pulses by comparing them to a fixed threshold. Because the input signal may be measured in millivolts and may also contain a significant amount of high-frequency noise, amplifying this signal and filtering out the noise can provide a more suitable signal on which to perform a comparison (waveform C). When a suitable threshold is provided, the result of the comparison is a digital signal that corresponds to the pulse train driving the LED for that channel when the beam path is clear (waveform D), and is low when the beam path is blocked.

Figure 3. The analog receiver can be implemented by a single ispPAC20 and a few discrete components. Programmable gain, filtering, and detection thresholds provide the flexibility to operate in many applications.

Other than a few discrete components to perform I-V conversion from the photodiode and AC coupling, all of the signal processing functions are performed by a Lattice Semiconductor ispPAC20 programmable analog IC. Two gain/filtering stages are used to boost and clean up the incoming signal, and threshold detection is implemented by one of the device’s comparators, with the actual threshold level being set by an onchip D/A converter.

Although this device allows the user to reconfigure the signal path to perform a variety of functions, its major strength in this application is its ability to vary the signal path parameters. Gain, filter corner frequencies, and the threshold trip point can be adjusted electronically, without jumpers, DIP switches, or component resoldering. In addition, the IC’s configuration and all parameter settings are stored permanently in E²CMOS nonvolatile memory, so no additional circuitry is needed to configure the device at power-on.

Digital Subsystems
Most of the complexity of this system, as is often the case, resides in the digital portion. Two cPLDs simplify the design process by allowing hierarchical design of a system and thus hiding much of its complexity. Another advantage of using programmable logic is that you get to design logic functions to do exactly what you want, as opposed to having to stitch together predesigned functions that may only partially meet your requirements.

The logic for this instrument was split between two Lattice Semiconductor MACH4 cPLD devices (ispM4A5-64/32). Each can implement logic designs with up to 64 flip-flops and several hundred logic gates. This partitioning decision was driven mainly by packaging options—these particular cPLDs come in a PLCC package (PLCC44). While Lattice Semiconductor makes cPLDs that could easily integrate this whole system many times over in a single device, using many of these larger devices would have required either fabricating a circuit board or buying relatively expensive socket or chip adapters. Either of these options would have violated the spirit of a do-it-yourself project. Because sockets for PLCC44 packages are inexpensive, and, more to the point, I happened to have some handy, cPLDs in this package got used. As it turned out, although the design had to be partitioned between the two devices, the split could be made relatively cleanly, with only a few interconnections between the two cPLDs.

Figure 4. The counter/display logic all fits inside a single user-configurable cPLD. Programmability allows designers to specify the logic they want, instead of merely settling for what is available. [Click for larger image]

Figure 4 shows the internal logic for the counter/display control cPLD. The primary feature of this design is the counter chain, which consists of five divide-by-10 and two divide-by-6 counters, providing a total of seven digits. This allows the measurement of times up to 59:59.999 min., with a resolution of 1 ms. The 1 kHz signal needed to count milliseconds is derived from a 40 kHz clock input coming from the master control cPLD.

In addition to the clock signal for incrementing the counter, we will need to start, stop, and reset it (to begin a new measurement cycle). Whenever the ENABLE_COUNT input is high, the counter will increment once every millisecond; when it is low, the counter will hold its present count. A high level on the RESET_COUNT line will reset the count back to 00:00.000 regardless of whether it is enabled or not.

Because a 7-digit LED display uses 49 segments (not counting the decimal points), and the cPLD that I chose provides only 32 I/O pins, I needed a time-multiplexed technique to drive the display. In a multiplexed display, each digit is controlled by one output line, while all the control lines for corresponding segments (A–G) are tied together. Each digit in the display is activated in sequence one at a time, and the segments corresponding to the activated digit are driven and illuminated. By sequencing the digits sufficiently fast, it is possible to make it appear that all of them are being continuously displayed.

Several functions are required to implement a multiplexed display system. First, there must be a way to scan through the display digits. This function is provided by a divide-by-8 counter that is also used to generate the 1 kHz timing signal. Its output is used to direct several activities. The first is digit selection, which is accomplished by a 3–8 decoder. At the same time, an 8–1 multiplexor is used to route the data from the appropriate digit in the counter to a BCD-to-7 segment decoder, which converts the binary-coded-decimal (BCD) data representing the digits into a pattern that will light the appropriate segments on the LED displays (e.g., converts 1001 to 9).

For aesthetic reasons, it is nice to blank leading “0” digits in the display, meaning that 4.734 s is displayed as 4.734, not 00:04.734. This makes our instrument a little bit more user friendly, and not looking like a countdown timer from a cheesy spy movie. To do this, I included blanking logic to look at the leading three digits (tens of minutes, minute, tens of seconds) and will selectively disable them depending on which ones are zero. When a digit is to be blanked, this circuit signals the BCD-to-7 segment decoder to shut off all of the segments. Additionally, an external blanking signal from the master control cPLD can shut off all the digits through the BLANK_DISPLAY input line.

Another nice feature is to have the counter stop counting once it reaches its maximum count (59:59.999). This provides a clear indication that the maximum time has expired, which might not be obvious if we simply let it roll over to “0.” To do this, terminal count detect logic looks at the output of all the digits, and signals the master control cPLD when this maximum count occurs through the OV_FLAG output line.

Figure 5. The master control logic provides central timing and control for the entire instrument, as well as applying a simple digital filtering function to the recovered optical signals. [Click for larger image]

The master control logic cPLD (see Figure 5) provides timed pulses to drive the IR LEDs that project the sensing beams, detects if a beam is broken, and provides state sequencing for the instrument as a whole. The master timing for the instrument derives from a 1 MHz external crystal oscillator. Because this is much faster than needed for any of the functions in this system, it is divided down to 40 kHz, used to generate and time the optical signals, and is further divided down to frequencies suitable for driving the counter and display electronics.

The IR LEDs are driven with a 25 µs pulse every 100 µs, each LED being pulsed at a different time. The pulse generator circuit sequences the LED pulses and also determines when to sample the detected signals coming from the analog receiver channels.

Because the received signal may contain spurious noise that can create false pulses, or suppress valid ones, incorporating some simple digital filtering into the missing pulse detectors can result in more reliable operation. In this design, a 4-bit counter is maintained in each missing pulse detector. Whenever a pulse is present, this counter increments by 1, reaching a maximum value of 1111 (15). Whenever a pulse is absent, this counter decrements, with a minimum value of 0000 (0). The most significant bit (MSB) of the counter is used to indicate the missing pulse condition, as it requires several missing pulses to cause the counter to decrement to 0111. This effectively prevents a few missing pulses from being recognized as a broken-beam event.

Because the optical beams use invisible IR radiation, it is difficult to align the IR LEDs and the photodiodes, or even to tell if the LEDs are illuminated. For a visual indication of proper beam alignment, each beam has two status indicators, displaying BEAM GOOD and BEAM BAD status. When the LED and photodiode for a given beam are properly aligned, the BEAM GOOD indicator will illuminate, and the BEAM BAD indicator will remain dark. In the case of total misalignment, or if the LED and photodiode are separated beyond their maximum range, the BEAM BAD LED will illuminate. In the case of a marginal signal, both LEDs will illuminate, with the relative degree of illumination providing an indication of alignment and signal strength.

The overall operation of the instrument is managed by the state controller logic. This circuitry implements the state machine shown in Figure 6 and provides for four operating states: RESET, ARMED, RUNNING, and DONE.

Figure 6. The master control's main state controller determines the overall behavior of the instrument in response to user commands and sensor input.

When the state controller is in the RESET state, the counter is reset and disabled. Additionally, the display is completely blanked. The RESET state can be entered at any time by closing the reset input switch.

Closing the arm switch, however, will move the controller from the RESET state into the ARM state. In the ARM state, the controller enables the display so it reads 0.000 and waits for beam A to be interrupted. When this event occurs, the controller moves into the RUNNING state where the counter is enabled and begins counting elapsed milliseconds. The controller also waits for beam B to be interrupted. When this occurs, it moves into the DONE state.

Photo 1. The elapsed-timer measurement system was constructed using point-to-point wiring on a 5 by 5 in. piece of perfboard. The RESET and ARM controls are on the lower left.

When in the DONE state, the controller disables the counter but does not reset it, so it holds the total elapsed time between beam A’s being broken and beam B’s being broken. It will continue to do so until the reset switch is closed.

To make the instrument state even more obvious, and because they look cool, I added several indicator LEDs to show state (see Photo 1). The red LED indicates the device is ARMED, green indicates RUNNING, and yellow indicates that the measurement cycle is finished. In the RESET state no LEDs are activated.

Summary
This article has presented a detailed design example of a simple instrument that can be used to measure speed by monitoring the time between two optical events. Although this embodiment was designed to measure times in the milliseconds-to-minutes range, the technique can easily be extended to elapsed times down into the microsecond or even nanosecond range. Operation in these domains would, however, require significant changes to the sensor and the analog signal processing circuits.

IspPAC, E²CMOS, MACH, and PCC-Designer are registered trademarks of, and ispLEVER is trademarked by, Lattice Semiconductor Corp.

SIDEBARS:

Speed Measurement in Action

Photo 2. One use for this instrument is at toy race-car competitions. In this application, the IR LEDs and photodiodes are embedded in the sides of the race track.

One obvious application for the type of instrument described here is timing races or other sporting events. The timing range and resolution (1 ms) that this device supports ideally suits it to clocking modern competitive events, where winners are often differentiated by hundredths of a second. One example is probably well known to many readers—the Pinewood Derby races, in which small variations in construction can yield significant differences in performance. A way to quantitatively characterize performance would allow contenders to test their designs before race day.

I outfitted a short length of track with a set of LEDs and photodiodes, spaced a foot apart (see Photo 2). Taking the reciprocal of the elapsed time as a racecar moves down the track yields its average speed in the foot-long measurement stretch.

Where Did the Gates Go?

Digital logic designs have traditionally been specified as schematic diagrams with wire connections between the inputs and outputs of the gates used. This approach made sense when logic was implemented from discrete transistor modules and ICs containing but a few gates apiece. For complex designs comprising thousands or even millions of gates, the schematic-based approach quickly runs out of steam. In these cases, Hardware Description Languages (HDLs) provide a more effective way to get from functional specification to working system.

As a simple example of how an HDL can be used to describe a logic diagram, consider the process I used to design the divide-by-6 counter used in this project. The first step was to build a state transition table, at which point I decided I needed three flip-flops to represent the count data. The next step was to derive state transition equations that cycled the flip-flops through my table. If I had been implementing this circuit in the 1970s and had had to build it from discrete logic ICs, my next step would have been to find appropriate parts and figure out how to wire them up, resulting in something comparable to the schematic shown in Figure 7.

Figure 7. Logic diagrams are a traditional way to describe a logic circuit, in this case the divide-by-6 counter used in the counter/display logic.

When using programmable logic, however, I need only to modify my equations to fit the syntax of the HDL I choose to use. The example offered is written in an HDL called ABEL. Note that in addition to the equations, I also need to specify my input and output connections, defining the counter as a reusable module.

MODULE HexCounter

“Synchronous divide-by-6 Counter with Sychronous Enable and Clear”

“ inputs - clk, reset, enable, terminal_count_in
 
      clock, rst,   tci  pin;

“ outputs - d2,d1,d0, terminal_count_out

      d2, d1, d0 pin istype ‘reg’;
      tco        pin istype ‘com’;

Equations

      tco = tci & d2 & (!d1) & d0;
 
      d0.d = (!rst) & (!tco) & (d0 $ (tci));
      d1.d = (!rst) & (!tco) & (d1 $ (tci & d0));
      d2.d = (!rst) & (!tco) & (d2 $ (tci & d1 & d0));
	  
      d0.clk  = clock;
      d1.clk  = clock;
      d2.clk  = clock;

END  “Module HexCounter”

ABEL is an example of a mature HDL. More recent and more powerful languages also exist, the most popular of which are VHDL and Verilog. In addition to letting you specify a design as equations, VHDL and Verilog will allow you to describe many systems at a very high level by writing behavioral specifications in a language similar to C.

What is Programmable Electronics?

Most people think of programming as something you do to computers, not electronic circuits. This has changed with the introduction of programmable logic circuits and programmable analog circuits. These devices let you reconfigure the interconnections and component values inside a finished IC to customize it to work in your particular application.

Figure 8. A PLD consists of an interconnection network that connects inputs to an AND_OR gate array.

The simplest type of programmable logic IC is called a PLD (programmable logic device), and consists of a matrix that connects a number of input signals to an and/or array. To be implemented, logic design equations need to be cast into a form that maps into this hardware (see Figure 8). This operation can be done automatically by CAD software, such as Lattice Semiconductor’s ispLever design system (which was used to develop the project described in this article). Once the software has completed this mapping operation, it generates a fuse-map telling the device programmer which of these crossbar links to connect or disconnect. A modern PLD can have hundreds of thousands of these links, and this level of integration allows it to implement designs equivalent to tens of thousands of discrete logic gates, all in a single IC.

Programmable analog circuits such as the ispPAC20 used in this project also provide the ability to configure connections among internal components, but because analog designs are crucially dependent on circuit parameters, the ispPAC20 also allows the designer to change characteristics such as gain, voltage, and frequency response. From an end-user standpoint, a programmable analog circuit is lower in complexity than a PLD; the design software (PAC-Designer) therefore allows engineers to directly manipulate connections and component values graphically on their computers, as shown in Screen 1.

Screen 1. Lattice Semiconductor's PAC-Designer software lets a designer configure the ispPAC20 and other ispPAC programmable analog circuits though a point-and-click user interface.

Because a programmable analog circuit is designed at a functional level (gain, filter corner frequency, etc.) as opposed to a component level, and design changes are fast and painless, it can often be easier to develop a viable design with programmable analog ICs than with traditional discrete analog circuits.